This book exhibits a unique way to explain nano materials, devices, analysis of its design parameters to meet the sub-nano-regime challenges for low power chip design. It highlights conventional and novel nano materials, devices and circuits, leakage current mitigation techniques and other important tradeoffs along with exhaustive analysis.
This book exhibits a unique way of explaining nanomaterials and devices and analyzing their design parameters to meet the sub-nanoregime challenges for low-power chip design. Since process variability, device sizing, and power supply scaling are ongoing challenges in very large-scale integration (VLSI) circuit designs, this book highlights the conventional and novel nanomaterials, devices and circuits, leakage current mitigation techniques, and other important trade-offs along with exhaustive analysis. More focus has been placed throughout the book on various trade-offs for high-speed and low-power VLSI devices and circuits co-design.
This book:
It is primarily written for senior undergraduates, graduate students, and academic researchers in the fields of electrical engineering, electronics and communications engineering, materials science, nanoscience, and nanotechnology.